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Intel unveils Foveros 3D chip stacking and new 10nm ‘chiplets’

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Intel has announced the successor to its 14nm CPU architecture. The Sunny Cove architecture is set to launch in both Core and Xeon server processors “later next year” and will be the first of their kind on the belated 10nm process.

Intel just made the announcement at its Architecture Day, during which its top execs – including VP of Core and Visual computing Raja Koduri – all got around to discuss Intel’s brand new segmented technical strategy. The model features six pillars: Process, Architecture, Memory, Interconnect, Security, and Software.






Intel made a series of announcements today as part of its “Architecture Day,” including a new CPU architecture called Sunny Cove, a next-generation integrated graphics solution, and perhaps most interesting, a 3D chip design breakthrough that could dictate how future processors are made.

Starting with Sunny Cove, the new architecture is bound for both Xeon server and Core consumer processors. Intel said it designed Sunny Cover to execute more operations in parallel, with new algorithms to reduce latency. “Sunny Cove enables reduced latency and high throughput, as well as offers much greater parallelism that is expected to improve experiences from gaming to media to data-centric applications,” Intel said.

We’ve
never heard Intel reference Sunny Cove before, so it was a bit of
surprise, especially with several other architectures already on the
roadmap. Our understanding is that the name Sunny Cove is a new way of
highlighting the base architecture, while there will still be product
codenames (eg, Ice Lake).

Sunny Cove is being built on a 10-nanometer manufacturing process. Intel had run into trouble with 10nm in the form of Cannon Lake, which is still on track to ship in volume at the end of next year. As Intel recently explained, however, its troubles with Cannon Lake “goes back to the early definitions of 10 nanometers in 2014” and the available lithography techniques back then.

Dr. Murthy Renduchintala, chief engineering officer at Intel and head of the company’s technology, systems architecture, and client group, had recently pointed out that Intel has separate teams working on 10nm and 7nm chip designs. His message seemed to be that Intel’s early troubles with 10nm don’t apply to 7nm. Now with the introduction of Sunny Cove, Intel seems to be indicating it has a firm grasp on 10nm design and (presumably) manufacturing as well.






According to various sources, including HotHardware and AnandTech,
Sunny Cove will also include dedicated registers and new instruction
sets to boost artificial intelligence, compression, processing, and
cryptography workloads. On top of it all, Sunny Cove is designed to
offer better branch prediction accuracy and larger cache allotments.

It
will be interesting to see what impact this has on Cannon Lake. Sunny
Cove is slated to arrive in the second half of next year, and one demo
chip showed “ICL-U” (Ice Lake U-series) on the heatsink, but the
codenames may be in a bit of a state of flux. If Sunny Cove delivers the
kind of IPC (instructions per clock) and overall improvements Intel
promises, we could see it cannibalizing Cannon Lake. We’re getting ahead
of ourselves, though.

gen 11 graphics
Image courtesy AnandTech

Pushing integrated graphics to 1 TFLOPS

To
go along with a new CPU architecture, Intel also unveiled a new round
of integrated graphics dubbed Gen11. It has 64 enhanced execution units
(EUs), which is more than double the current generation Gen9 solution
with 24 EUs.

“The new integrated graphics architecture is expected
to double the computing performance-per-clock compared to Intel Gen9
graphics. With >1 TFLOPS performance capability, this architecture is
designed to increase game playability,” Intel said.

To put that in perspective, Intel is looking at more than doubling the performance of its GT2 graphics variant, so the HD Graphics 630 as an example currently offers a peak 460 GFLOPS. And there’s still potential for larger performance improvements thanks to architectural changes.






We
don’t expect Gen11 to compete with high-end discrete graphics cards,
but with the significant bump in EUs, it should offer much better
performance than Intel’s current solutions. Gen11 is slated to arrive in
10nm processors starting next year (which we assume to mean Sunny Cove /
 Ice Lake).

3d face face stacking
Image courtesy AnandTech

3D chip stacking

Arguably
the most interesting thing Intel announced had nothing to do with Sunny
Cove or new graphics that are in the pipeline, but a new 3D chip
packaging technology called Foveros.

3D stacking is not inherently
new—the technique is already used in memory products. However, what
Intel unveiled is the industry’s first 3D stacking of logic chips, which enables logic-on-logic integration for the first time.

“The technology provides tremendous flexibility as designers seek to ‘mix and match’ technology IP blocks with various memory and I/O elements in new device form factors. It will allow products to be broken up into smaller ‘chiplets‘, where I/O, SRAM and power delivery circuits can be fabricated in a base die and high-performance logic chiplets are stacked on top,” Intel explains.






Gizmodo
likens it to building a multi-level house, as opposed to a single-level
ranch home. It’s a “radical re-architecture of systems-on-chips
(SoCs),” according to Intel, and it’s something the company has been
working on for a very long time. Ramune Nagisetty, director of process
and product integration at Intel and one of the leads on 3D stacking,
told Gizmodo that Intel had been working on this “a lot longer than
anything related to 10 nanometers.”

From a technical standpoint, one of the big advantages to 3D stacking
is being able to swap out transistors and fit ones into a package that
are most appropriate for the application.

“The transistor that’s
best for a desktop gaming CPU is not necessarily the best transistor for
a GPU. Similarly, you need different transistors for running 5G and
interconnectivity,” Intel’s graphics boss Raja Koduri said.
“Before, we used to just take the best compromise of all of the
silicon. Now, we can take processes that are best for the function and
put them all together on a single package. And because we have very high
bandwidth between these chips, they will function exactly as if they
are a single chip.”

This isn’t some theoretical breakthrough that may never see the light of day. Just the opposite, Intel says it expects to launch a range of products using Foveros in the second half of 2019.






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